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83006hkim b8-9266 no.a0135-1/21 ver.1.42 LC877C64C,lc877c56c lc877c48c,lc877c40c lc877c32c,lc877c24c overview the lc877c00 series are an 8-bit single chip microcontroller with the following on-chip functional blocks. : ? cpu: operable at a minimum bus cycle time of 83.3ns ? on-chip 64k-24k bytes rom ? on-chip ram: 2048/1536 bytes ? lcd controller / driver ? 16 bit timer/counters (can be divided into 8-bit units) ? 16 bit timer / pwm (can be divided into two 8-bit timers) ? four 8-bit timer with prescalers ? timer for use as date / time clock ? synchronous serial i/o port (with automatic block transmit / receive function) ? asynchronous / synchronous serial i/o port ? 2 channel 12bit pwm ? 12-channel 8-bit ad converter ? high-speed clock counter ? system clock divider ? small signal detector ? 20 source 10-vectored interrupt system all of the above functions are fabricated on a single chip. features ? rom ? 65536 8 bits (LC877C64C) ? 57344 8 bits (lc877c56c) ? 49152 8 bits (lc877c48c) ? 40960 8 bits (lc877c40c) ? 32768 8 bits (lc877c32c) ? 24576 8 bits (lc877c24c) ordering number : ena0135 cmos ic internal 64k/56k/48k/40k/32k/24k-byte rom and 2048/1536-byte ram 8-bit 1-chip microcontroller any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before usingany sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated val ues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein.
LC877C64C/56c/48c/40c/32c/24c no.a0135-2/21 ? ram ? 2048 9 bits (LC877C64C/56c) ? 1536 9 bits (lc877c48c/40c/32c/24c) ? minimum instruction cycle time ? 250 ns (12mhz) v dd =4.5 to 5.5v ? 300 ns (10mhz) v dd =2.8 to 5.5v ? 750 ns (4mhz) v dd =2.2 to 5.5v ? ports ? input/output ports data direction programmable for each bit individually: 20 (p1n, p70 to p73, p8n) data direction programmable in nibble units: 8 (p0n) (when n-channel open drain output is selected, data can be input in bit units.) ? input ports: 2 (xt1, xt2) ? output ports: 2 (pwm2, pwm3) ? lcd ports segment output: 32 (s00 to s15, s24 to s39) common output: 4 (com0 to com3) bias terminals for lcd driver: 3 (v1 to v3) other functions input/output ports: 32 (pan, pbn, pdn, pen) input ports: 7 (pln) ? oscillator pins: 2 (cf1, cf2) ? reset pin: 1 ( res ) ? power supply: 6 (v ss 1-3, v dd 1-3) ? lcd controller ? seven display modes are available (static, 1/2, 1/3, 1/4 duty 1/2, 1/3 bias) ? segment output and common output can be switched to general purpose input/output ports. ? small signal detection (mic signals etc) ? counts pulses with the level whic h is greater than a preset value ? 2 bit counter ? timers ? timer 0: 16 bit timer / counter with capture register mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register mode 1: 8 bit timer with 8 bit programmab le prescaler and 8 bit capture register + 8 bit counter with 8-bit capture register mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register mode 3: 16 bit counter with 16 bit capture register ? timer 1: pwm / 16 bit timer/ counter with toggle output function mode 0: 8-bit timer with 8-bit prescaler (and toggle output) + 8-bit timer / co unter with 8-bit prescaler (and toggle output) mode 1: 2 channel 8-bit pwm with 8-bit prescaler mode 2: 16-bit timer / counter with 8-bit prescaler (and toggle output) (toggle output also possible using the lower order 8 bits) mode 3: 16-bit timer with 8-bit prescaler (and toggle output) (the lower order 8 bits can be used as pwm output) ? timer 4: 8-bit timer with 6-bit prescaler ? timer 5: 8-bit timer with 6-bit prescaler ? timer 6: 8-bit timer with 6-bit prescaler (and toggle output) ? timer 7: 8-bit timer with 6-bit prescaler (and toggle output) ? base timer 1) the clock signal can be selected from any of the following : sub-clock (32.768khz crystal oscillator), system clock, and prescaler output from timer 0 2) interrupts of five different time intervals are possible.
LC877C64C/56c/48c/40c/32c/24c no.a0135-3/21 ? high-speed clock counter ? countable up to 20mhz clock (when using 10mhz main clock) ? real time output ? sio ? sio 0: 8 bit synchronous serial interface 1) lsb first / msb first is selectable 2) internal 8 bit baud-rate generator (fastest clock period 4 / 3 tcyc) 3) consecutive automatic data communication (1 to 256 bits) ? sio 1: 8 bit asynchronous / synchronous serial interface mode 0: synchronous 8 bit serial io (2-wire or 3-wire, transmit clock 2 to 512 tcyc) mode 1: asynchronous serial io (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tcyc) mode 2: bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tcyc) mode 3: bus mode 2 (start detection, 8 data bits, stop detection) ? ad converter: 8 bits 12 channels ? pwm: 2 channels multi-frequency 12-bit pwm ? remote control receiver circuit (connect ed to p73 / int3 / t0in terminal) ? noise rejection function (noise rejection filter?s time constant can be selected from 1 / 32 / 128 tcyc) ? watchdog timer ? the watching time period is determined by an external rc. ? watchdog timer can produce interrupt or system reset ? interrupts: 20 sources, 10 vectors 1) three priority (low, high and highest) multiple interrupts are supported. during interrupt handling, an equal or lower priority interrupt request is postponed. 2) if interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. in the case of equal priority levels, the vect or with the lowest address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l 4 0001bh h or l int3/base timer0 /base timer1 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0 8 0003bh h or l sio1 9 00043h h or l adc/mic/t6/t7 10 0004bh h or l port 0/t4/t5/pwm2, pwm3 ? priority level: x > h > l ? for equal priority levels, vector with lowest address takes precedence. ? subroutine stack levels: 1024 levels max (LC877C64C/56c) 768 levels max (lc877c48c/40c/32c/24c) stack is located in ram.
LC877C64C/56c/48c/40c/32c/24c no.a0135-4/21 ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? on-chip rc oscillation for system clock use. ? cf oscillation for system clock use. (rf built in, rd external) ? crystal oscillation low speed system clock use. (rf built in, rd external) ? on-chip frequency variable rc oscillation circuit for system clock use. ? system clock divider ? low power consumption operation is available ? minimum instruction cycle time (300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2 s, 38.4s, 76.8s can be switched by program (when using 10mhz main clock) ? standby function ? halt mode halt mode is used to reduce power consumption. during the halt mode, program execution is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop). 1) oscillation circuits are not stopped automatically. 2) released by the system reset or interrupts. ? hold mode hold mode is used to reduce power consumption. program execution and peripheral circuits are stopped. 1) cf, rc, x?tal and multi-frequency rc os cillation circuits stop automatically. 2) released by any of the following conditions. (1) low level input to the reset pin (2) specified level input to one of int0, int1, int2 (3) port 0 interrupt ? x?tal hold made x?tal hold mode is used to reduce power consumption. program execution is stopped. all peripheral circuits excep t the base timer are stopped. 1) cf, rc and multi-frequency rc osc illation circuits stop automatically. 2) crystal oscillator operation is kept in its state at hold mode inception. 3) released by any of the following conditions (1) low level input to the reset pin (2) specified level input to one of int0, int1, int2 (3) port 0 interrupt (4) base-timer interrupt ? package form ? qfp80 (14 14): lead-free type ? tqfp80j (12 12): lead-free type ? development tools ? evaluation chip: lc87ev690 ? emulator: eva62s + ecb876600d + sub877100 + pod80qfp(14 14) or pod80sqfp ice-b877300 + sub877100 + pod80qfp(14 14) or pod80sqfp ? flash rom version: lc87f7cc8a
LC877C64C/56c/48c/40c/32c/24c no.a0135-5/21 package dimensions package dimensions unit : mm (typ) unit : mm (typ) 3255 3290 pin assignment sanyo : qfp80 (14 14) ?lead-free type? sanyo : tqfp80j (12 12) ?lead-free type? v1/pl4 v2/pl5 v3/pl6 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s15/pb7 top view p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/micin p70/int0/t0lcp/an8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 v ss 2 v dd 2 s14/pb6 s13/pb5 s12/pb4 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1/pa1 s0/pa0 p73/int3/t0in p72/int2/t0in p71/int1/t0hcp/an9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 com0/pl0 com1/pl1 com2/pl2 com3/pl3 pwm2 v ss 3 v dd 3 pwm3 p00 p01 p02 p03 p04 p05 p06 p07 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 LC877C64C/ lc877c56c/ lc877c48c/ lc877c40c/ lc877c32c/ lc877c24c 120 21 40 41 60 80 61 (1.25) 0.2 0.5 0.125 12.0 12.0 14.0 14.0 0.5 (1.0) 0.1 1.2max sanyo : tqfp80j(12x12) sanyo : qfp80(14x14) 14.0 14.0 17.2 17.2 0.15 0.1 3.0max 0.25 0.65 (0.83) (2.7) 0.8 1 20 21 40 41 60 80 61
LC877C64C/56c/48c/40c/32c/24c no.a0135-6/21 system block diagram interrupt control stanby control ir pla rom clock generator cf rc x?tal pc bus interface port 0 port 1 sio0 sio1 timer 0 (high speed clock counter) timer 1 base timer lcd controller int0 to 3 noise rejection filter port 3 port 8 pwm adc weak signal detector acc b register c register psw rar ram stack pointer alu timer 6 timer 7 timer 4 timer 5 mrc watchdog timer
LC877C64C/56c/48c/40c/32c/24c no.a0135-7/21 pin description pin name i/o function option v ss 1, v ss 2, v ss 3 - ? power supply (-) no v dd 1, v dd 2 v dd 3 - ? power supply (+) no port0 p00 to p07 i/o ? 8bit input/output port ? data direction programmable in nibble units ? use of pull-up resistor can be specified in nibble units ? input for hold release ? input for port 0 interrupt ? other functions p05: clock output (system clock / can selected from sub clock) p06: timer 6 toggle output p07: timer 7 toggle output yes port1 p10 to p17 i/o ? 8bit input/output port ? data direction programmable for each bit ? use of pull-up resistor can be specified for each bit individually ? other pin functions p10 sio0 data output p11 sio0 data input or bus input/output p12 sio0 clock input/output p13 sio1 data output p14 sio1 data input or bus input/output p15 sio1 clock input/output p16: timer 1 pwml output p17: timer 1 pwmh output/buzzer output yes ? 4bit input/output port ? data direction can be specified for each bit ? use of pull-up resistor can be specified for each bit individually ? other functions p70: int0 input/hold releas e input/timer0l capture input/output for watchdog timer p71: int1 input/hold release input/timer0h capture input p72: int2 input/hold release input/tim er 0 event input/timer0l capture input p73: int3 input(noise rejection filter attac hed)/timer 0 event input/t imer0h capture input ad input port: an8(p70), an9(p71) ? interrupt detection selection rising falling rising and falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable port7 p70 to p73 i/o no continued on next page.
LC877C64C/56c/48c/40c/32c/24c no.a0135-8/21 continued from preceding page. pin name i/o function description option port8 p80 to p87 i/o ? 8bit input/output port ? input/output can be specified for each bit individually ? other functions: ad input port: an0 to an7 small signal detector input port: micin(p87) no s0/pa0 to s7/pa7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pa) no s8/pb0 to s15/pb7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pb) no s24 /pd0 to s31/pd7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pd) no s32/pe0 to s39/pe7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pe) no com0/pl0 to com3/pl3 i/o ? common output for lcd ? can be used as general purpose input port (pl) no v1/pl4 to v3/pl6 i/o ? lcd output bias power supply ? can be used as general purpose input port (pl) no pwm2 o pwm2 output port no pwm3 o pwm3 output port no res i reset terminal no xt1 i ? input for 32.768khz crystal oscillation ? other functions: general-purpose input port ad input port: an10 ? when not in use, connect to v dd 1 no xt2 i/o ? output for 32.768khz crystal oscillation ? other functions: general purpose input port ad input port: an11 ? when not in use, set to oscillation mode and leave open no cf1 i input terminal for ceramic oscillator no cf2 o output terminal for ceramic oscillator no
LC877C64C/56c/48c/40c/32c/24c no.a0135-9/21 port output types port form and pull-up resistor options are shown in the following table. port status can be read even when port is set to output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable (note 1) p00 to p07 each bit 2 nch-open drain none 1 cmos programmable p10 to p17 each bit 2 nch-open drain programmable p70 - none nch-open drain programmable p71 to p73 - none cmos programmable p80 to p87 - none nch-open drain none s0/pa0 to s15/pb7 s24/pd7 to s39/pe7 - none cmos programmable com0/pl0 to com3/pl3 - none input only none v1/pl4 to v3/pl6 - none input only none pwm2, pwm3 - none cmos none xt1 - none input only none xt2 - none output for 32.768khz crystal oscillation none note 1: attachment of port0 programmable pull-up resistors is controllable in nibble units (p00 to 03, p04 to 07). *1: connect as follows to reduce noise on v dd . v ss 1, v ss 2 and v ss 3 must be connected together and grounded. *2: the power supply for the internal memory is v dd 1 but it uses the v dd 2 as the power supply for ports. when the v dd 2 is not backed up, the port level does not become ?h? even if the port latch is in the ?h? level. therefore, when the v dd 2 is not backed up and the port latch is ?h? level, the port level is unstable in the hold mode, and the back up time becomes shorter because the through current runs from v dd to gnd in the input buffer. if v dd 2 is not backed up, output ?l? by the program or pull the port to ?l? by the external circuit in the hold mode so that the port level becomes ?l? level and unnecessary current consumption is prevented. lsi v dd 1 back-up capacitors *2 v dd 2 v dd 3 v ss 2 v ss 1 power supply v ss 3
LC877C64C/56c/48c/40c/32c/24c no.a0135-10/21 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 supply voltage for lcd vlcd v1/pl4, v2/pl5, v3/pl6 v dd 1=v dd 2=v dd 3 -0.3 v dd input voltage v i port l xt1, xt2, cf1, res -0.3 v dd +0.3 input/output voltage v io (1) ? ports 0, 1, 7, 8 ? ports a, b, d, e ? pwm2, pwm3 -0.3 v dd +0.3 v ioph(1) ports 0,1 ? cm os output selected ? current at each pin -10 ioph(2) ports 71,72,73 current at each pin -5 peak output current ioph(3) ? ports a, b, d, e ? pwm2, pwm3 current at each pin -5 iomh(1) ports 0,1 ? cmos output selected ? current at each pin -7.5 iomh(2) ports 71, 72, 73 current at each pin -3 average output current (note 1-1) iomh(3) ? ports a, b, d, e ? pwm2, pwm3 current at each pin -3 ioah(1) ? ports 0, 1 ? pwm2, pwm3 total of all pins -25 ioah(2) port 7 total of all pins -10 ioah(3) ports a, b, total of all pins -25 ioah(4) ports d, e total of all pins -25 high level output current total output current ioah(5) ports a, b, d, e total of all pins -45 iopl(1) ports 0, 1 current at each pin 20 iopl(2) ports 7,8 current at each pin 10 peak output current iopl(3) ? ports a, b, d, e ? pwm2, pwm3 current at each pin 10 ioml(1) ports 0, 1 current at each pin 15 ioml(2) ports 7, 8 current at each pin 7.5 average output current (note 1-1) ioml(3) ? ports a, b, d, e ? pwm2, pwm3 current at each pin 7.5 ioal(1) ? ports 0, 1 ? pwm2, pwm3 total of all pins 45 ioal(2) ports 7, 8 total of all pins 15 ioal(3) ports a, b total of all pins 45 ioal(4) ports d, e total of all pins 45 low level output current total output current ioal(5) ports a, b, d, e total of all pins 80 ma qfp80(14 14) 381 maximum power consumption pd max tqfp80j(12 12) ta = -30 to +70 c 325 mw operating temperature range topr -30 +70 storage temperature range tstg -55 +125 c note 1-1: average output current indi cates average value for 100ms term.
LC877C64C/56c/48c/40c/32c/24c no.a0135-11/21 allowable operating range at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit v dd (1) 0.245s tcyc 200s 4.5 5.5 v dd (2) 0.294s tcyc 200s 2.8 5.5 operating supply voltage range v dd (3) v dd 1=v dd 2=v dd 3 0.735s tcyc 200s 2.2 5.5 supply voltage range in hold mode vhd v dd 1 keep ram and register data in hold mode. 2.0 5.5 v ih (1) ? ports 0, 8 ? ports a, b, d, e, l output disable 2.2 to 5.5 0.3v dd +0.7 v dd v ih (2) ? port 1 ? ports 71, 72, 73 ? p70 port input/interrupt output disable 2.2 to 5.5 0.3v dd +0.7 v dd v ih (3) p87 small signal input output disable 2.2 to 5.5 0.75v dd v dd v ih (4) port 70 watchdog timer output disable 2.2 to 5.5 0.9v dd v dd input high voltage v ih (5) xt1, xt2, cf1, res 2.2 to 5.5 0.75v dd v dd v il (1) 4.0 to 5.5 v ss 0.15v dd +0.4 v il (2) ? ports 0, 8 ? ports a, b, d, e, l output disable 2.2 to 4.0 v ss 0.2v dd v il (3) 4.0 to 5.5 v ss 0.1v dd +0.4 v il (4) ? port 1 ? ports 71, 72, 73 ? p70 port input/interrupt output disable 2.2 to 4.0 v ss 0.2v dd v il (5) port 87 small signal input output disable 2.2 to 5.5 v ss 0.25v dd v il (6) port 70 watchdog timer output disable 2.2 to 5.5 v ss 0.8v dd -1.0 input low voltage v il (7) xt1, xt2, cf1, res 2.8 to 5.5 v ss 0.25v dd v 4.5 to 5.5 0.245 200 2.8 to 5.5 0.294 200 operation cycle time (note 2-1) tcyc 2.2 to 5.5 0.735 200 s 4.5 to 5.5 0.1 12 2.8 to 5.5 0.1 10 ? cf2 open ? system clock divider :1/1 ? external clock duty = 50 5% 2.2 to 5.5 0.1 4 4.5 to 5.5 0.2 24.4 2.8 to 5.5 0.2 20 external system clock frequency fexcf(1) cf1 ? cf2 open ? system clock divider :1/2 2.2 to 5.5 0.2 8 mhz fmcf(1) 12mhz ceramic resonator oscillation see fig. 1. 4.5 to 5.5 12 fmcf(2) 10mhz ceramic resonator oscillation see fig. 1. 2.8 to 5.5 10 fmcf(3) 4mhz ceramic resonator oscillation see fig. 1. 2.2 to 5.5 4 fmrc rc oscillation 2.2 to 5.5 0.3 1.0 2.0 fmmrc cf1, cf2 frequency variable rc oscillation source oscillation 2.2 to 5.5 16 mhz oscillation frequency range (note 2-2) fsx?tal xt1, xt2 32.768khz crystal resonator oscillation see fig. 2. 2.2 to 5.5 32.768 khz note 2-1: oscillation frequency and operation cycle time (tcyc) rerationship: 1/1divide-3/fmcf, 1/2divide-6/fmcf note 2-2: the parts value of oscillation ci rcuit is shown in table 1 and table 2.
LC877C64C/56c/48c/40c/32c/24c no.a0135-12/21 electrical characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ? ports 0, 1, 7, 8 ? ports a, b, d, e, l ? pwm2, pwm3 ? output disabled ? pull-up resister off. ? v in =v dd (including off state leak current of the output tr.) 2.2 to 5.5 1 i ih (2) res v in =v dd 2.2 to 5.5 1 i ih (3) xt1, xt2 when configured as an input port. v in =v dd 2.2 to 5.5 1 i ih (4) cf1 v in =v dd 2.2 to 5.5 15 high level input current i ih (5) p87/an7/micin small signal input v in =v bis +0.5v (v bis : bias voltage) 4.5 to 5.5 5 10 20 i il (1) ? ports 0, 1, 7, 8 ? ports a, b, d, e, l ? pwm2, pwm3 ? output disabled ? pull-up resister off. ? v in =v ss (including off state leak current of the output tr.) 2.2 to 5.5 -1 i il (2) res v in =v ss 2.2 to 5.5 -1 i il (3) xt1,xt2 when configured as an input port. v in =v ss 2.2 to 5.5 -1 i il (4) cf1 v in =v ss 2.2 to 5.5 -15 low level input current i il (5) p87/an7/micin small signal input v in =v bis -0.5v (v bis : bias voltage) 4.5 to 5.5 -20 -10 -5 a v oh (1) i oh =-1.0ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) ports 0, 1: cmos output option i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (4) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (5) port 7 i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (6) i oh =-1.0ma 4.5 to 5.5 v dd -1 v oh (7) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 high level output voltage v oh (8) ? ports a, b, d, e, ? pwm2, pwm3 i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.6ma 3.0 to 5.5 0.4 v ol (3) ports 0, 1 i ol =1.0ma 2.2 to 5.5 0.4 v ol (4) i ol =1.6ma 3.0 to 5.5 0.4 v ol (5) ports 7, 8 i ol =1.0ma 2.2 to 5.5 0.4 v ol (6) i ol =1.6ma 3.0 to 5.5 0.4 low level output voltage v ol (7) ? ports a, b, d, e, ? pwm2, pwm3 i ol =1.0ma 2.2 to 5.5 0.4 vodls s0 to s15, s24 to s39 i o =0ma vlcd, 2/3vlcd, 1/3vlcd level output see fig. 8. 2.2 to 5.5 0 0.2 lcd output voltage regulation vodlc com0 to com3 i o =0ma vlcd, 2/3vlcd, 1/2vlcd 1/3vlcd level output see fig. 8. 2.2 to 5.5 0 0.2 v rlcd(1) resistance per one bias resistor see fig. 8. 2.2 to 5.5 60 lcd bias resistor rlcd(2) ? resistance per one bias resistor ? 1/2r mode see fig. 8. 2.2 to 5.5 30 k ? continued on next page.
LC877C64C/56c/48c/40c/32c/24c no.a0135-13/21 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit 4.5 to 5.5 15 35 80 resistance of pull-up mos tr. rpu ? ports 0, 1, 7 ? ports a, b, d, e v oh =0.9v dd 2.2 to 4.5 18 50 150 k ? vhys(1) ? ports 1, 7 ? res 2.2 to 5.5 0.1v dd hysterisis voltage vhys(2) port 87 small signal input 2.2 to 5.5 0.1v dd v pin capacitance cp all pins ? all other terminals connected to v ss . ? f=1mhz ? ta=25 c 2.2 to 5.5 10 pf input sensitivity vsen port 87 small signal input 2.2 to 5.5 0.12v dd vp-p serial input/output characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 6. 1 input clock high level pulse width tsckha(1) sck0(p12) ? continuous data transmission/reception mode ? see fig. 6. ? (note 4-1-2) 2.2 to 5.5 4 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig. 6. 1/2 tsck serial clock output clock high level pulse width tsckha(2) sck0(p12) ? continuous data transmission/reception mode ? cmos output selected ? see fig. 6. 2.2 to 5.5 tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tcyc data setup time tsdi(1) 2.2 to 5.5 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.2 to 5.5 0.03 tdd0(1) ? continuous data transmission/reception mode ? (note 4-1-3) 2.2 to 5.5 (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 2.2 to 5.5 1tcyc +0.05 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11) (note 4-1-3) 2.2 to 5.5 (1/3)tcyc +0.15 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
LC877C64C/56c/48c/40c/32c/24c no.a0135-14/21 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig. 6. 2.2 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected ? see fig. 6. 2.2 to 5.5 1/2 tsck data setup time tsdi(2) 2.2 to 5.5 0.03 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.2 to 5.5 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.2 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use.
LC877C64C/56c/48c/40c/32c/24c no.a0135-15/21 pulse input conditions at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) int4(p30 to p33) int5(p34 to p35) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 2.2 to 5.5 1 tpih(2) tpil(2) int3(p73) (noise rejection ratio is 1/1.) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 2.2 to 5.5 2 tpih(3) tpil(3) int3(p73) (noise rejection ratio is 1/32.) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 2.2 to 5.5 64 tpih(4) tpil(4) int3(p73) (noise rejection ratio is 1/128.) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 2.2 to 5.5 256 tpil(5) tpil(5) micin(p87) ? condition that signal is accepted to small signal detection counter. 2.2 to 5.5 1 tcyc high/low level pulse width tpil(6) res ? condition that reset is accepted 2.2 to 5.5 200 s ad converter characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 15.62 (tcyc= 0.488 s) 97.92 (tcyc= 3.06 s) ad conversion time=32 tcyc (when adcr2=0) (note 6-2) 3.0 to 5.5 23.52 (tcyc= 0.735 s) 97.92 (tcyc= 3.06 s) 4.5 to 5.5 18.82 (tcyc= 0.294 s) 97.92 (tcyc= 1.53 s) s conversion time tcad ad conversion time=64 tcyc (when adcr2=1) (note 6-2) 3.0 to 5.5 47.04 (tcyc= 0.735 s) 97.92 (tcyc= 1.53 s) analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p80) to an7(p87), an8(p70), an9(p71), an10(xt1), an11(xt2) vain=v ss 3.0 to 5.5 -1 a note 6-1: absolute precision does not include quantizing error (1/2 lsb). note 6-2: conversion time means time from executing ad conversion instruction to loading complete digital value to register.
LC877C64C/56c/48c/40c/32c/24c no.a0135-16/21 consumption current characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddop(1) ? fmcf=12mhz ceramic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? system clock: cf 12mhz oscillation ? frequency variable rc oscillation stopped ? internal rc oscillation stopped. ? divider: 1/1 4.5 to 5.5 7 12 iddop(2) 4.5 to 5.5 5.5 9 iddop(3) 3.0 to 3.6 3.1 5.6 iddop(4) ? fmcf=10mhz ceramic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? system clock: cf 10mhz oscillation ? frequency variable rc oscillation stopped ? internal rc oscillation stopped. ? divider: 1/1 2.8 to 3.0 2.2 3.8 iddop(5) 4.5 to 5.5 2.5 4 iddop(6) 3.0 to 3.6 1.2 2.5 iddop(7) ? fmcf=4mhz ceramic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? system clock: cf 4mhz oscillation ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider:1/1 2.2 to 3.0 0.9 1.8 iddop(8) 4.5 to 5.5 0.55 2.1 iddop(9) 3.0 to 3.6 0.3 1.4 iddop(10) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? frequency variable rc oscillation stopped ? system clock: rc oscillation ? divider:1/2 2.2 to 3.0 0.2 1 iddop(11) 4.5 to 5.5 1.2 3.5 iddop(12) 3.0 to 3.6 0.65 2.2 iddop(13) ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz crystal oscillation ?internal rc oscillation stopped. ?system clock: 1mhz with frequency variable rc oscillation ?divider:1/2 2.2 to 3.0 0.4 1.6 ma iddop(14) 4.5 to 5.5 27 65 iddop(15) 3.0 to 3.6 11 45 current consumption during normal operation (note 7-1) iddop(16) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? system clock: 32.768khz ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider:1/2 2.2 to 3.0 7 32 a iddhalt(1) halt mode ? fmcf=12mhz ceramic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? system clock: cf 12mhz oscillation ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider: 1/1 4.5 to 5.5 2.5 5.3 iddhalt(2) 4.5 to 5.5 2 4.2 iddhalt(3) 3.0 to 3.6 1.1 2.3 iddhalt(4) halt mode ? fmcf=10mhz ceramic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? system clock: cf 10mhz oscillation ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider: 1/1 2.8 to 3.0 0.7 1.5 iddhalt(5) 4.5 to 5.5 1.2 2.6 iddhalt(6) 3.0 to 3.6 0.65 1.4 current consumption during halt mode (note 7-1) iddhalt(7) v dd 1 =v dd 2 =v dd 3 halt mode ? fmcf=4mhz ceramic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? system clock: cf 4mhz oscillation ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider: 1/1 2.2 to 3.0 0.38 0.88 ma note 7-1: the currents through the output transi stors and the pull-up mos transistors are ignored. continued on next page.
LC877C64C/56c/48c/40c/32c/24c no.a0135-17/21 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddhalt(8) 4.5 to 5.5 0.28 1 iddhalt(9) 3.0 to 3.6 0.15 0.7 iddhalt(10) halt mode ? fmcf=0hz (oscillation stop) ? fsx?tal=32.768khz crystal oscillation ? system clock: rc oscillation ? frequency variable rc oscillation stopped ? divider: 1/2 2.2 to 3.0 0.1 0.5 iddhalt(11) 4.5 to 5.5 1 2.9 iddhalt(12) 3.0 to 3.6 0.55 1.8 iddhalt(13) halt mode ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? internal rc oscillation stopped. ? system clock: 1mhz with frequency variable rc oscillation ? divider :1/2 2.2 to 3.0 0.35 1.4 ma iddhalt(14) 4.5 to 5.5 19 50 iddhalt(15) 3.0 to 3.6 6.2 30 current consumption during halt mode (note 7-1) iddhalt(16) v dd 1 =v dd 2 =v dd 3 halt mode ? fmcf=0hz (oscillation stop) ? fsx?tal=32.768khz crystal oscillation ? system clock: 32.768khz ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped ? divider: 1/2 2.2 to 3.0 3.6 20 iddhold(1) 4.5 to 5.5 0.025 10 iddhold(2) 3.0 to 3.6 0.015 7 current consumption during hold mode iddhold(3) hold mode ? cf1=v dd or open (when using external clock) 2.2 to 3.0 0.009 6 iddhold(4) 4.5 to 5.5 16 45 iddhold(5) 3.0 to 3.6 5.5 25 current consumption during date/time clock hold mode iddhold(6) v dd 1 date/time clock hold mode ? cf1=v dd or open (when using external clock) ? fmx?tal=32.768khz crystal oscillation 2.2 to 3.0 3 15 a note 7-1: the currents through the output transi stors and the pull-up mos transistors are ignored.
LC877C64C/56c/48c/40c/32c/24c no.a0135-18/21 characteristics of a sample main system clock oscillation circuit the characteristics in the table bellow is based on the following conditions: (1) use the standard evaluation board sanyo has provided. (2) use the peripheral parts with indicated value externally. (3) the peripheral parts value is a recommended value of oscillator manufacturer table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rf1 [ ? ] rd1 [ ? ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz murata cstce12m0g52-r0 (10) (10) open 470 4.5 to 5.5 0.05 0.15 internal c1, c2 cstce10m0g52-r0 (10) (10) o pen 1.0k 2.8 to 5.5 0.05 0.15 10mhz murata cstls10m0g53-b0 (15) (15) open 680 2.8 to 5.5 0.05 0.15 internal c1, c2 cstcr4m00g53-r0 (15) (15) o pen 3.3k 2.2 to 5.5 0.05 0.15 4mhz murata cstls4m00g53-b0 (15) (15) o pen 3.3k 2.2 to 5.5 0.05 0.15 internal c1, c2 the oscillation stabilizing time is a period until the oscillation becomes stable after v dd becomes higher than minimum operating voltage (see figure 4). characteristics of a sample subs ystem clock oscillator circuit the characteristics in the table bellow is based on the following conditions: (1) use the standard evaluation board sanyo has provided. (2) use the peripheral parts with indicated value externally. (3) the peripheral parts value is a recommended value of oscillator manufacturer table 2 characteristics of a sample subsystem clock oscillator circuit with a crystal oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf2 [ ? ] rd2 [ ? ] operating voltage range [v] typ [s] max [s] remarks 32.768khz seiko epson mc-306 18 18 open 560k 2.2 to 5.5 1.3 3.0 applicable cl value =12.5pf the oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the hold mode (see figure 4). note : since the circuit pattern affects the oscillation frequency, place the oscillation- related parts as close to the oscillation pins as possible with the shortest possible pattern length. figure 1 ceramic oscillator circuit figure 2 crystal oscillator circuit figure 3 ac timing measurement point 0.5v dd cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf2 c1 rd1 c2 cf rf1
LC877C64C/56c/48c/40c/32c/24c no.a0135-19/21 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization times operating v dd lower limit power suppl y res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd 0v internal rc oscillation cf1, cf2 xt1, xt2 state hold reset signal hold reset signal valid tmscf tmsx?tal hold halt hold reset signal absent
LC877C64C/56c/48c/40c/32c/24c no.a0135-20/21 figure 5 reset circuit figure 6 serial i/o output waveforms figure 7 pulse input timing signal waveform c res v dd r res res note : determine the value of c res and r res so that the reset signal is present for a period of 200 s after the supply voltage goes beyond the lower limit of the ic?s operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk : datain : dataout : dataout : datain : sioclk : dataout : datain : sioclk : tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transfer period (sio0 only) data ram transfer period (sio0 only)
LC877C64C/56c/48c/40c/32c/24c no.a0135-21/21 figure 8 lcd bias resistor ps vlcd sw : on ( vlcd=v dd ) 2/3vlcd 1/2vlcd 1/3vlcd sw : on/off (programmable) v dd gnd rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d this catalog provides information as of august, 2006. specifications and information herein are subject to change without notice. specifications of any and all sanyo semiconductor pr oducts described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify s ymptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high- quality high-reliability products. however, any and all semiconductor products fail with some probabi lity. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property . when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor produc ts (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording , or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circui t parameters) herein is for example only; it is not guaranteed for volume production. sanyo semicondu ctor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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